1. Technical Field
Exemplary embodiments relate generally to a semiconductor integrated circuit, and more particularly to a semiconductor memory apparatus and a test circuit therefor.
2. Related Art
Generally, when data are written in a memory cell of a semiconductor memory apparatus, the data input through input/output pads are written into cells by a write driver. Further, when data are read from memory cells, the data in the memory cells are transferred to a sense amplifier, output amplified data through the input/output pads.
FIG. 1 is a configuration diagram of a general semiconductor memory apparatus.
As shown in FIG. 1, a semiconductor memory apparatus 100 includes a memory cell array 101, an address input buffer 103, a predecoder 105, a column decoder 107, a block decoder 109, a row decoder 111, a data input and output buffer 113, a sense amplifier 115, a write driver 117, and a controller 120.
The memory cell array 101 includes a plurality of memory cells connected between word lines and bit lines.
The address input buffer 103 receives external addresses and converts the received external addresses into internal addresses. The predecoder 105 primarily decodes the internal addresses and then provides the primarily decoded internal addresses to the column decoder 107, the block decoder 109 and the row decoder 111. The column decoder 107 selects word lines to be accessed according to predecoding results. The block decoder 109 selects blocks to be accessed according to the predecoding results. Similarly, the row is decoder 111 selects bit lines to be accessed according to the predecoding results.
The data input and output buffer 113 is coupled to a plurality of data input and output pads (e.g., DQ pads).
When the data writing operation is performed, the data read from the selected memory cells of the memory cell array 101 are amplified in the sense amplifier 115 according to control signals generated from the controller 120 and then output to the DQ pad through the data input and output buffer 113. When the data writing operation is performed, the data input from the DQ pad according to the control signal generated from the controller 120 are provided to the write driver 117 through the input and output buffer 113 and the data are transferred to the memory cells selected from the write driver 117.
The controller 120 includes a first input buffer 121 configured to be driven by a chip select signal /CS, a second input buffer 123 configured to be driven by a write enable signal /WE, a third input buffer 125 configured to be driven by an output enable signal /OE, a write pulse generator 127 configured to generate a write pulse WDEN in response to an output signal of the second input buffer 123, and a read pulse generator 129 configured to generate a read pulse OEN in response to an output signal of the third input buffer 125. The write pulse generator 127 also generates a data input and output buffer enable signal BUFEN and provides the generated data input and output buffer enable signal BUFEN to the data input and output buffer 113. The read pulse generator 129 generates a sense amplifier enable signal SAEN and provides the generated sense amp enable signal SAEN to the sense amplifier 115.
As such, the semiconductor memory apparatus reads the data through the sense amplifier and writes the data through the write driver.
However, when newly developed memory cells are applied to the semiconductor memory apparatus, a verification process of the developed memory cells needs to be performed, but it is difficult to secure reliability of the verification of reading/writing data through the sense amplifier and the write driver. Therefore, when the reading/writing operation is operated through the sense amplifier and the write driver, the cells needs to be evaluated after verifying variables of the reading/writing path, the memory cell array, and the controller, and thus it takes much time to test the cells.